Raj Thummar | Design Verification Engineer

Every chip is different. Every chip has bugs worth finding.

Nov 2026 – PresentMTS Silicon Design EngineerSECIP teamOttawaHybrid

Back at AMD

On the SECIP team in Ottawa from November 2026. More here soon.

Jul 2025 – Oct 2026SoC Design Verification EngineerAI accelerator SoCsOttawaRemote

Secure boot for AI chips

Verified the boot ROM on two Tenstorrent SoCs. It is the first code a chip runs and the one part that can’t be patched after tape-out, so every path had to hold: flash discovery, image authentication, key revocation, anti-rollback.

Built the ZeBu emulation flow, plus a cocotb/pytest setup that runs the same tests in simulation and on the emulator.
Got the boot test running at gate level on the SDF-annotated netlist, with its own regression.

Aug 2022 – Jul 2025Sr. Silicon Design EngineerWired IP Solutions GroupOttawaHybrid

Ethernet that resends its own errors

Worked on 800G Ethernet IP for data-centre networks. Owned verification of Link Level Retry for Ultra Ethernet: when a frame gets corrupted on the wire, the link resends it from a local buffer instead of waiting on the slow end-to-end path.

Retransmission, acknowledgements and timeouts, checked against IEEE 802.3 and the Ultra Ethernet spec.

Sep 2020 – Aug 2022FPGA Verification EngineerRockport Networks, now CerioOttawaRemote

Putting packets back in order

Rockport’s network split traffic across many paths at once, so packets showed up out of order. Led verification of the Reorder Manager, the block that lines them back up.

Built the block-level UVM testbench: sequences, scoreboard, checkers and constrained-random tests.
Wrote the test plan and coverage spec, triaged regressions daily and closed coverage.

The tools, and what they are for.

coverage gap → more tests

Reading the spec01 · spec

What must always be true
What can go wrong, and how it should react
Open questions back to the architects

Turn each requirement into something to check and something to measure. Most bugs start as a misread requirement.

Verification plan02 · plan

Every feature, and the test that exercises it
Checkers, assertions and the coverage that proves it
Sign-off criteria: what “done” means

Written and reviewed before the testbench is built, and the measure of when verification is finished.

Register plan02 · plan

Reset values for every register
Access rules: read-only, read-write, write-1-to-clear
A register model (UVM RAL) to drive and check them

The chip’s control registers are what software talks to, so each one is checked against the register map.

UVM environment03 · build

env
├─ agent: seqr · drv · mon
├─ scoreboard  expected vs actual
└─ coverage collector

A reusable testbench: drivers feed the design, monitors watch it, a scoreboard checks every result.

Assertions (SVA)03 · build

assert property (
  req |-> ##[1:3] ack);

Rules that watch the design on every clock cycle and flag the exact moment one is broken.

Constrained-random tests04 · test

constraint c_len {
  len inside {[64:9216]};
}

SystemVerilog tests that pick random inputs within the rules, to reach cases nobody thought to write by hand.

Python · cocotb · pytest04 · test

@cocotb.test()
async def sanity(dut):
    await RisingEdge(dut.clk)

Tests written in Python that can run unchanged in simulation and on an emulator.

Synopsys VCS05 · debug

$ vcs -sverilog -f tb.f
$ ./simv +UVM_TESTNAME=sanity_test

Compiles the design and the testbench together and runs the simulation.

Verdi05 · debug

$ verdi -ssf waves.fsdb &
# trace X back to its driver

Shows every signal over time, so a wrong value can be followed back to the line that caused it.

Jenkins CI/CD06 · regress

stage('Lint')  { sh 'make lint' }
stage('Smoke') { sh 'make smoke' }

Runs the regressions automatically: build, lint gate, smoke tests, release.

Regression triage06 · regress

$ grep -l UVM_ERROR */sim.log
seed_4021/sim.log

Sort the failures, separate real bugs from noise, and report each with a test that reproduces it.

Hardware emulation (ZeBu)06 · regress

simulation

emulation

The same design mapped onto emulation hardware, many times faster than simulation, for long tests like a full boot.

Gate-level simulation06 · regress

# real gate delays from SDF
$ vcs ... -sdf max:dut:top.sdf

Re-runs tests on the final wired-up netlist, with real timing, before the chip is made.

Functional coverage07 · close

coverpoint len {
  bins min = {64};
  bins max = {9216}; }

Measures which planned scenarios have really been tested, so “done” means done.

Coverage closure07 · close

functional

code

assertions

Sign-off: every planned scenario hit, the code exercised, and every gap explained before the chip is made.